1. Field of the Invention
The present invention relates to a SiP (System in a Package) semiconductor apparatus that incorporates a logic chip and a memory chip into a common package and a test method for the same.
2. Description of Related Art
BIST (Built-In Self-Test) is a test method for a semiconductor apparatus that conducts self-test using a test pattern generator, a test pattern compressor, a comparator or the like placed inside a device. In the BIST, a test pattern generator generates a test pattern to be supplied to a test target circuit, a test pattern compressor compresses an output pattern from the test target circuit, and a comparator compares the compressed test pattern with an expected output pattern, thereby testing the test target circuit.
Japanese Unexamined Patent Application Publication No. 2003-77296 (Ishikawa) discloses a SiP semiconductor apparatus that incorporates a logic chip and a memory chip into a common package. The semiconductor apparatus places a memory chip test circuit (BIST circuit) and a selector-input/output circuit inside a logic chip to thereby enable testing of the memory chip by the BIST.
FIG. 9 shows the overall configuration of the semiconductor apparatus taught by Ishikawa. The semiconductor apparatus incorporates a logic chip 202 and a memory chip 203 into a common package 201. The logic chip 202 includes a logic circuit 202A, a memory chip test circuit 204, and a selector-input/output circuit 202C. The selector-input/output circuit 202C switches selection so as to activate the logic circuit 202A during normal operation and to activate the memory chip test circuit 204 during testing of the memory chip 203, so that the selected circuit accesses the memory chip 203.
A test method of the memory chip 203 is that the memory chip test circuit 204 in the logic chip 202 generates test data, address and control signals for the memory chip 203, compares write data and read data to the memory chip 203, and outputs a comparison result. Thus, the semiconductor apparatus of this related art places a BIST circuit to conduct BIST inside the logic chip 202.
FIG. 10 is an internal block diagram of the memory chip test circuit 204 shown in FIG. 9. This circuit activates an initialization circuit 246, a self-test circuit 247 and a test mode setting circuit 248 sequentially in response to a START input signal and a control data signal 249. Then, in the circuit, a memory chip control circuit 241 generates WRITE data W-DATA, address Add and a control signal CNT for the memory chip 203 and supplies these signals to the memory chip 203 to thereby perform WRITE operation. During READ operation of the memory chip 203, a determination circuit 242, an OR gate 243 and a flip-flop 244 compare READ data R-DATA output from the memory chip 203 with expected value data EXV generated in the memory chip control circuit 241 and output a comparison result through a test result signal terminal 250.
FIGS. 11 and 12 respectively show first and second exemplary internal configurations of the selector-input/output circuit 202C shown in FIG. 9. The circuit selects a memory access signal S1 from the logic circuit 202A during normal operation, a test access signal S2 from the memory chip test circuit 204 during memory chip test, and a signal S3 from a functional macro 231 during logic circuit test to thereby make an access to the memory chip 203.
Specifically, the selector-input/output circuit 202C shown in FIG. 11 includes a selector 251 to select one from the memory access signal S1, the test access signal S2 and the signal S3 from the functional macro 231, a flip-flop 252 to temporarily hold those signals, and an output buffer 253 to output the signals held in the flip-flop 252 through output terminals 223, 224 and 225. The selector 251 is configured to be capable of selecting the signal S3 from the functional macro 231 in addition to the memory access signal S1 and the test access signal S2 described above. The selector 251 selects one from the signals S1, S2 and S3 according to a select signal, which is not shown.
The selector-input/output circuit 202C also includes an input buffer 254 to input read data DATA from the memory chip 203 and a flip-flop 255 to hold the data. The output of the flip-flop 255 is supplied to the logic circuit 202A, the memory chip test circuit 204, and the functional macro 231 in the logic circuit 202A.
On the other hand, in the selector-input/output circuit 202C shown in FIG. 12, a selector is divided into a selector 251B to select one from the test access signal S2 and the signal S3 for logic circuit test and a selector 251A to select one from the signal selected by the selector 251B and an access signal S1 from the logic circuit 202A during normal operation. The output of the selector 251A is supplied directly to the output buffer 253. Further, a flip-flop 252 to temporarily hold the access signal S1 during normal operation, a flip-flop 255 to temporarily hold the test access signal S2 from the memory chip test circuit, and a flip-flop 256 to temporarily hold the signal S3 for logic circuit test in a wafer state are placed in the previous stage of the selectors 251A and 251B. An input circuit configuration is such that the output of the input buffer 254 is supplied to the flip-flops 252, 255 and 256.
In such a SiP semiconductor apparatus that incorporates a logic chip and a memory chip into a common package, a memory cell configuration (row/column configuration) of a memory chip differs by memory vendor. Further, the row/column configuration of a memory, even from the same vendor, differs if a manufacturing process (corresponding design rule) is different. It is thus difficult to test a memory chip with different row/column configuration using one BIST circuit. This causes deterioration of quality and increase in circuit size. As a technique to enable testing of a memory chip with different row/column configuration, Japanese Unexamined Patent Application Publication No. 2004-158098 (Tatsumi), for example, discloses a technique of inputting a test signal to a memory chip through an external terminal and then monitoring an output signal from the memory chip.
FIG. 13 shows a semiconductor apparatus taught by Tatsumi. As shown in FIG. 13, according to Tatsumi, a SiP semiconductor apparatus 310 includes a logic chip 311 and a memory chip 312. In the SiP semiconductor apparatus 310, the logic chip 311 includes a test circuit 316 to thereby enable testing of the memory chip 312 at relatively low speed using an external terminal.
Specifically, the logic chip 311 includes a logic circuit 315 and the test circuit 316. The logic chip 311 is directly connected with an external connection terminal through a line 313 and also connected with the memory chip 312 through a line 317. When a mode selection signal inside the external connection terminal indicates test mode, access is made from the external connection terminal to the memory circuit 314 through a line 318, the test circuit 316 and the line 317, not through the logic circuit 315. Accelerated life test and Multi-Bit Test that expands test data, writes the expanded data into the memory circuit 314 and compresses read data to thereby determine if it is defective or non-defective are performed. It is also possible to make a direct access from the external connection terminal to the memory circuit 314 through the line 318, the test circuit 316 and the line 317 to perform BIST upon power-ON or after that.
FIG. 14 is a block diagram showing a specific configuration of the test circuit 316 shown in FIG. 13. The test circuit 316 includes a memory test circuit 321 and a selection circuit 322 and uses the line 317 as a common access path to the memory circuit 314. During normal operation, an output signal from the logic circuit 315 is output to the line 317 from the line 319 through the test circuit 316. During testing, necessary test signals (324 to 329) are input to and output from the line 317 from the line 318 through the test circuit 316. The test signals involve an access control signal 324, a mode signal 325, a read/write address signal 326, a test write data signal 327, a test data signal 328, and a determination result signal 329. These signals are used to access the memory circuit 314 to thereby perform accelerated life test, Multi-Bit test and self-diagnostic test (BIST).
FIG. 15 is an example of a specific circuit configuration of the test circuit 316 shown in FIG. 14. The test circuit 316 includes flip-flops (FFs) 371 and 378, selectors 372 and 374, a decoder 377, an accelerated life test circuit 375, a degeneration circuit 376, and an expansion circuit 373. The test circuit 316 inputs/outputs signals with the logic circuit 315 and the external connection terminal. Specifically, the test circuit 316 selects by the selector 372 either the output of the logic circuit 315 (during actual operation) or the signal processed from the signal from the external connection terminal (during testing) and makes an access to the memory circuit (DRAM) 314.
In the semiconductor apparatus disclosed in Ishikawa, a logic chip includes a BIST circuit to test a memory chip as described above. It is thereby possible to test the memory chip by the BIST at an actual operation speed of the memory chip. However, it is necessary to form a BIST circuit that corresponds to the row/column configuration of the memory chip. This is because an optimal number of rows and columns of a memory, even with the same number of bits, can vary by manufacturing process (corresponding design rule), and it is thus difficult for one BIST to conform to a memory chip with a different number of rows and columns in the test that is conducted based on the number of rows and columns intended to marking test, checkerboard test or the like.
In the semiconductor apparatus disclosed in Tatsumi, a logic chip includes a test circuit to test a memory chip by receiving a test signal from an external terminal during test mode. Because a test signal is input from outside, it is possible to conduct a desired test without altering an external circuit regardless of the number of rows and columns. However, signal delay of a test signal input to a memory chip from a test data signal input terminal and signal delay of a test result signal output from the memory chip to the test data signal terminal during testing can hinder testing at an actual operation speed of the memory chip. Specifically, if a test frequency is high, it is difficult to perform high-speed testing at a desired operation frequency due to signal delay inside the logic chip.